In the integrated circuit (IC) industry today, billions of semiconductor devices are built on a single substrate, generally referred to as a wafer. The current demands for high density and performance associated with ultra large-scale integration entail the use of submicron features, increased transistor and circuit speeds, and improved reliability.
Defects, such as line and bridge defects, also known as nano-bridging, are one of the larger sources of wafer defects during the lithography step for advanced nodes. Bridge defects are especially prevalent in extreme ultraviolet (EUV) lithography, where dose limitation and high photon absorption rate make the process particularly prone to bridge defects at the bottom of the features due to an underdeveloped photoresist. Previous post-processing methods to remove bridge defects are undesirable because the methods also consume the photoresist. Consuming the photoresist indiscriminately results in a loss in resist height, making it difficult to transfer etch patterns.
Therefore, there is an ongoing need to more effectively correct bridge and line defects in semiconductor devices.